The present invention relates to a semiconductor memory device and, mainly, to a technique which is effective when utilized in a dynamic RAM (Random Access Memory) including switch MOSFETs between a sense amplifier and bit lines.
The dynamic RAM, which is intended to raise the speed of the sense amplifier by turning OFF the selected side of a shared select MOSFET temporarily to lighten the load on the sense amplifier, has been disclosed in Japanese Patent Laid-Opens Nos. 64-73596, 5-62463 and 8-106781. In Japanese Patent Laid-Open No. 4-167293, on the other hand, there is disclosed a dynamic RAM. In this dynamic RAM, switch MOSFETs which are interposed between the input/output nodes of the sense amplifier and complementary bit lines, are first set to the unselect level at the time of starting the amplification of the sense amplifier, so that the sense amplifier and the complementary bit lines are isolated to start the amplifying operations. After a column selection, the gate voltage of the switch MOSFETs is set to an intermediate potential to perform the operations in parallel to output one of the sense amplifier amplification signals to the IO lines and to restore the other amplification signal in the bit lines. After this, the gate voltage of the switch MOSFETs is returned to the select level so that the one amplification signal is re-stored through the bit lines in the memory cells.
Here, the terminlogy "MOS(Metal Oxide Semiconductor)FET" includes a "MIS(Metal Insulated Semiconducor)FET according to general recognition, and widely refers to a field effect transistor.